A Domain-Specific RISC-V Processor Design for Automatic Differentiation.

Abstract

This thesis presents the development of a RISC-V processor design, which is capable of evaluating multiple partial derivatives at once in parallel to the evaluation of an original mathematical function that is given the form of a computer program. This process is known as ``automatic differentiation'' (AD). The novel processor design extends existing RISC-V processor designs and is implemented via high-level synthesis on an FPGA. The FPGA serves as a platform for emulation and verification of the general idea. Our first prototypical implementations serve as a proof-of-concept. The design is validated by executing multiple small example applications, including a non-linear optimization problem which is solved via gradient descent, where the gradient constitutes 15 partial derivatives which are successfully computed in our hardware inherently parallel to the evaluation of the original function. Comparing our hardware-based approach to AD with established software-based alternatives demonstrates that our approach reduces the number of required instructions to solve a given AD-related problem significantly and slightly increases overall performance. This overall increase in performance comes at the cost of increased hardware resource utilization and a significant loss in clock frequency on the FPGA. Throughout the thesis, we discuss current limitations of our design, point towards potential workarounds for these limitations, and suggest extensions that would enhance the design even further in future work.